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Friday, October 25 • 9:30am - 10:00am
Status Update of COLO Project - Xiaowei Yang, Huawei and Will Auld, Intel

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We have presented the idea of coarse grain lock-stepping (COLO) virtual machiens for non-stop service in last year's xen summit. We have made significant progress in the past year and submitted the patch series to the community. It is a good time for us to present the latest status to the community and call for participation.


Will Auld

Performance Architect, Principal Engineer, Intel

Xiaowei Yang

Xiaowei Yang, Huawei. Xiaowei is an architect of Huawei Virtualzation Platform. He is responsible for the technical development of virutalization projects.

Friday October 25, 2013 9:30am - 10:00am
Kilsyth Hall Edinburgh International Conference Centre

Attendees (3)